1. Field of the Invention
This invention relates generally to the synchronization of periodic signals, such as clock signals. More particularly, the invention relates to a phase detector for reducing noise.
2. Description of the Related Art
Many high speed electronic systems possess critical timing requirements that dictate the need to generate a periodic clock waveform possessing a precise timing relationship with respect to some reference signal. The improved performance of computing integrated circuits and the growing trend to include several computing devices on the same board present a challenge with respect to synchronizing the time frames of all the components.
While the operation of various components in the system should be highly synchronized, i.e., the maximum skew in time between the significant edges of the internally generated clocks of the components should be minimized, it is not enough to feed the reference clock of the system to these components. This is because different chips may have different manufacturing parameters, which, when taken together with additional factors such as ambient temperature, voltage, and processing variations, may lead to large differences in the phases of the respective chip generated clocks. Conventionally, synchronization is achieved by using digital delay locked loop (DDLL) circuits to detect the phase difference between clock signals of the same frequency and produce a digital signal related to the phase difference. By feeding back the phase difference-related signal to control a delay line, the timing of one clock signal is advanced or delayed until its rising edge is coincident with the rising edge of a second clock signal.
The phase differences are typically detected by a phase detector included in the digital delay locked loop circuit. The phase detector compares an input, or reference, signal to a feedback signal and then generates a signal proportional to the phase difference between the reference and feedback signals. The signal proportional to the phase difference is then provided to a so-called “delay line” that may introduce a variable delay into the delay path of the input signal. Conventional digital delay lines include a number of discrete delay elements, each of which may be capable of introducing a single unit delay into the delay path. For example, a conventional delay element may be an inverter that introduces a unit delay of about 200 picoseconds into the delay path. Thus, the phase detector signal typically corresponds to a series of “up” and “down” signals that indicate that a delay element should be introduced into, or removed from, the delay path, respectively.
When the phase difference between the input signal and the reference signal becomes close to, or less than, one unit delay, conventional phase detectors generate a series of alternating “up” and “down” signals. If several clock cycles are required for a signal to propagate through the delay path and feedback to the phase detector, the series of adjustments indicated by the alternating “up” and “down” signals may create noise that may cause loop stability problems in the digital delay locked loop. The series of adjustments performed in response to the alternating signals may also cause the phase of the output clock signal to advance and retreat on successive clock cycles, creating noise, such as jitter, in the output clock signal. Noise in the output clock signal may reduce the stability of, or cause an error in, the digital device relying on the output clock.